The present application relates to the fabrication of interconnect structures for semiconductor devices and, more particularly to methods for minimizing metal contamination and dielectric damage that typically occur during the formation of interconnect structures.
Integrated circuits (ICs) commonly use metal interconnects to connect semiconductor devices such as, for example, transistors, on the ICs. Metal interconnects are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with a metal, which is then planarized using, for example, a chemical-mechanical planarization (CMP) process.
The damascene approach requires incorporation of low-k dielectric materials (e.g., materials with dielectric constants less than about 4.0) to reduce capacitive coupling between adjacent interconnects. The high capacitive coupling can cause cross talk and/or resistance-capacitance (RC) delay, thus degrading the overall performance of the ICs. However, directly patterning a low-k dielectric material layer during the conventional damascene process normally results in deformation in etch pattern profile due to the low mechanical strength of the low-k dielectric materials. The deformed etch pattern profile adversely impacts the reliability of the ICs through its effect on the continuity and conformality of metal deposition in a later process step. As integrated circuit technology continues to scale down to smaller technology nodes, methods that allow good profile and dimension control of damascene pattern are needed.